The Technology Map Viewer (Post-Mapping) does not load the schematic of the design netlist when Analysis & Synthesis is complete - The Technology Map Viewer (Post-Mapping) does not load the schematic of the design netlist when Analysis & Synthesis is complete Description In the Quartus II software version 15.0, the Technology Map Viewer (Post-Mapping) fails to load the schematic of your design netlist when Analysis & Synthesis or the full design compilation is complete. The failure occurs because the Partition Merge process did not run. Resolution To run the Partition Merge processs, navigate to Processing > Start > Start Partition Merge once Analysis & Synthesis is complete. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']