What is the Instruction Register (IR) length of the Hard Processor System (HPS) JTAG pins on Cyclone V and Arria V SoC devices? - What is the Instruction Register (IR) length of the Hard Processor System (HPS) JTAG pins on Cyclone V and Arria V SoC devices? Description The HPS JTAG pins are not intended for boundary scan for Cyclone® V and Arria® V SoC devices. The HPS JTAG pins do not have a Boundary-Scan Description Language (.bsd) file, but if you have this port included in your JTAG chain, you will need to know the IR length. The IR length is 4 bits and the BYPASS instruction is 0xF (the bypass instruction is always all ones according to IEEE1149.1). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']