F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer - F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point send an answer , when I follow this write with a Configuration Read type 0 to read the BAR 0 of the End point I do not receive any answer. Is there any configuration which avoid the read data to go through the F-Tile ? Is there any problem with my Configuration Read type 0 command I have attached the STP file as well. Thank you for help. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Thank you Rong. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer You may need to recheck your design if a given valid is not seen by the IP. Here is a F-Tile RP reading another FPGA's VID. Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, When I trig on tx_st_valid, it never trigs. Do you have a PCIe specialist I can have access ? Thanks. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer I think you should trigger tx_st_valid. Regards, Rong Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Rong, I recall you the bus access sequence I show you is working with R-Tile. This is exactly the same sequence. So why It is not working with F-Tile ? Thank you. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Rong, Can you translate your last sentence in bus access to the RP IP in order I understand what you mean. Thank you. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer The F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR. Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0). Regards, Rong Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, All these accesses are done on the configuration space of the RP Pcie directly through the configuration bus. There is no type 0 or type 1 concern to have. Thanks. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer I think something is mixed here. Most actions should be done to the type1 config register. But the mem space enable should be written to type0 command. Read @82h to get Link Rate and Link width Write 00h at @18h Read @18h to check previous Write Write 01h at @19h Read @19h to check previous Write Write 01h at @1Ah Read @1Ah to check previous Write Write 00h at @1Bh Read @1Bh to check previous Write Write 06h at @04h <------------------------to type0 command Read @04h to check previous Write Regards, Rong Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, You are welcome. No I cannot read the EP_VID and EP_DID. When I am doing a read on this register I did not get an answer. Do you have a Pcie Protocole Analyzer ti check what is produce by tve F_Tile ? Thanks. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Thanks for the detailed info. This is very helpful since checking these reg values manually takes a lot of time. Are you able to read EP VID and DID, configuration offset 0x0? Regards, Rong Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Thank you Rong. Do you need my project ? I can encrypted it and send it to you if you want ? The sequence I am doing is the following : Using the configuration Bus : Read @82h to get Link Rate and Link width Write 00h at @18h Read @18h to check previous Write Write 01h at @19h Read @19h to check previous Write Write 01h at @1Ah Read @1Ah to check previous Write Write 00h at @1Bh Read @1Bh to check previous Write Write 06h at @04h Read @04h to check previous Write Read @78h to get RP Dev CTRL register Read @79h to get RP Dev CTRL register Read @7Ah to get RP Dev CTRL register Read @7Bh to get RP Dev CTRL register Read @74h to get RP CAP Payload Max Using the Avalon Stream Bus Configuration Write type 0 End Point BAR0 with FFFFFFFFh @10h Wait for completion (Completion received) Configuration Read ype 0 End Point BAR0 @10h Wait for completion (Completion NEVER received. Please let me know if you need any other information. Thanks for help. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer I'm trying to setup a F-Tile RP test env to check. Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, Any news, I am blocked now. Can you have the help from another person ? Thank you. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, When using a Configuration Write or Read Request the address is compose of : Bus Number(7:) & Device Nb(7:0) & Ext_Reg(7:0) & reg Nb(7:0). So what you see is the Bus Number=01h and Reg Nb=10h. By the way, I have the same behaviour with the address=00h (Device ID & Vendor ID) in the Configuration Space. Thanks for help. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Thanks for the clarification. I misunderstood your request in the previous message. From the stp, you were reading addr 0x01000010, not 0x10. Regards, Rong Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hello Rong, Nice to see you again. BAR0 in address 10h, is in the Configuration Space not in the Memory Space, so you have to use a Configuration Access. I am using the same access with my Agilex7i-R-Tile board and it is working. So this is very strange it is not working on the Agilex-7F board. Thanks for help. Serge Replies: Re: F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer Hi Serge, When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh >>This doesn't look right. For a BAR test, I think you should use MWr and MRd. Regards, Rong