Why is the rx_pcs_ready signal not getting asserted and causing a timeout in the F-Tile Ethernet Multirate FPGA IP simulation during initial link up with Base Profile and Startup Profile set to 200GE variants? - Why is the rx_pcs_ready signal not getting asserted and causing a timeout in the F-Tile Ethernet Multirate FPGA IP simulation during initial link up with Base Profile and Startup Profile set to 200GE variants? Description In the F-Tile Ethernet Multirate FPGA IP simulation, during the initial link up with the Base profile and a startup profile set at 200GE variants, the test becomes unresponsive, leading to a hang in the Quartus® Prime Pro Edition Software version 24.1. Despite the TX lane being stable and the VIP behavior appearing normal, the rx_pcs_ready signal is not getting asserted. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16023378159 False ['F-Tile Ethernet Multirate IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']