Does Stratix V QDRII/ SDRAM Controller at full rate have timing closure issue? - Does Stratix V QDRII/ SDRAM Controller at full rate have timing closure issue?
Description Yes, you might experience out of box timing violations with Stratix® V QDRII/ at full rate. This issue will be fixed in a future Quartus® II software and IP version. Resolution To workaround this issue, in the SDC file locate these lines: if {} { set_clock_uncertainty -to [get_clocks _*] -add -hold 0.200 set_clock_uncertainty -to [get_clocks _*] -add -hold 0.100 set_clock_uncertainty -to [get_clocks _*] -add -hold 0.160 } and change them to if {} { set_clock_uncertainty -to [get_clocks _*] -add -hold 0.400 set_clock_uncertainty -to [get_clocks _*] -add -hold 0.150 set_clock_uncertainty -to [get_clocks _*] -add -hold 0.225 set_clock_uncertainty -to [get_clocks _*] -add -setup 0.200 }
Custom Fields values:
['novalue']
Troubleshooting
novalue
False
['novalue']
['FPGA Dev Tools Quartus II Software']
novalue
11.1.1
['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document