Why is the rx_st_valid signal not asserted in the Intel® L- and H-tile Avalon® Streaming for PCI Express* IP when receiving an Unsupported Request (UR) completion? - Why is the rx_st_valid signal not asserted in the Intel® L- and H-tile Avalon® Streaming for PCI Express* IP when receiving an Unsupported Request (UR) completion? Description Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, you may encounter the above problem when receiving an Unsupported Request (UR) completion on physical functions(PF) 2 and 3. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 1508832544 False ['Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.1 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']