CoaXPress-over-Fiber Bridge Device IP core - Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer. Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Arria® 10 GX FPGA Intel® Cyclone® 10 GX FPGA The CoaXPress-over-Fiber Device Bridge IP Core allows to connect a CoaXPress Device IP Core to an nGMII (10/25 Gbps Media Independent Interface) bus inside an FPGA. nGMII, as defined in IEEE Std 802.3 Clause 46, is the main access to the 10/25G Ethernet physical layer. Delivered as working reference design (when licensed with S2I CoaXPress Device IP Core) and extensive simulation testbench. Aerospace Defense Industrial Medical CoaXPress-over-Fiber Bridge Device IP core Key Features Extension for CoaXPress 2.1 compliant IP for camera applications Offering Brief Yes Yes No Yes Encrypted VHDL VHDL Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Arria® 10 GX FPGA Intel® Cyclone® 10 GX FPGA No Yes JIIA Compliance Test 24.3.1 Offering Brief Production a1JUi0000060o2zMAA What's Included Reference Design for Altera Evaluation Kit Ordering Information CoaXPress-over-Fiber Bridge Device IP core Direct a1JUi0000060o2zMAA Production Intellectual Property (IP) a1MUi00000BO8rrMAD a1MUi00000BO8rrMAD Select 2025-10-31T22:00:00.000+0000 Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer. Partner Solutions