Do dedicated clock input pins on Banks 3A/8A and Banks 3B/8B support single-ended I/O standards for Cyclone IV device? - Do dedicated clock input pins on Banks 3A/8A and Banks 3B/8B support single-ended I/O standards for Cyclone IV device? Description Yes, dedicated clock input pins (CLKIN) on Banks 3A/8A and Banks 3B/8B support single-ended I/O standard for Cyclone® IV GX devices when the clock is not used as a transceiver input. If the CLKIN on Banks 3A/8A and Banks 3B/8B is used as a transceiver REFCLK, the CLKIN only supports differential I/O standards and VCC_CLKIN on the Bank must be set to 2.5 V. If CLKIN on Banks 3A/8A and Banks 3B/8B is used as a non-transceiver PLL REFCLK, it can support single-ended I/O standards. For CLKIN on Banks 3B/8B, only positive terminal inputs support single-ended I/O standards. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']