In the Platform Designer, why are the Triple Speed Ethernet IP core clock names not described in the user guide? - In the Platform Designer, why are the Triple Speed Ethernet IP core clock names not described in the user guide? Description The Triple Speed Ethernet User Guide describes the clock names used in the parameter editor configuration. The Platform Designer uses the following clock names: control_port_clock_connection pcs_mac_tx_clock_connection pcs_mac_rx_clock_connection receive_clock_connection transmit_clock_connection Resolution The following Platform Designer clock names are equivalent to the clock names in the parameter editor: control_port_clock_connection -> clk pcs_mac_tx_clock_connection -> tx_clk pcs_mac_rx_clock_connection -> rx_clk receive_clock_connection -> ff_rx_clk transmit_clock_connection -> ff_tx_clk Related Articles In Qsys, why are the Triple Speed Ethernet(TSE) clock names for Arria 10 not described in the User Guide? Custom Fields values: ['novalue'] Troubleshooting 2205755647 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.0 ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']