Customizing the 28-nm Hard IP for PCI Express - 35 Minutes In this class, you will learn how to use the Qsys system design tool to build a PCI Express® Endpoint or Root Port design containing the Cyclone® V, Arria® V or Stratix® Hard IP for PCI Express. You will see how to select options in the Hard IP parameter editor to customize the Hard IP per your specific design requirements. As an alternative, you will discover how the Quartus® II IP Catalog can be used as another method for building your PCI Express design. Targeted devices: Cyclone® V, Arria® V, and Stratix® V FPGAs Course Objectives At course completion, you will be able to: Use the Platform Designer system design tool to create a PCI Express design in an Altera® 28 nm FPGA using the Hard IP for PCI Express Customize your Hard IP instance using IP parameter editor Create a PCI Express design using the Quartus II IP Catalog flow Skills Required Some understanding of the PCI Express Protocol specification is helpful, but not required Familiarity with common high-speed transceiver architecture or viewing the following transceiver basics course or attending the Building Gigabit interfaces in Altera® transceiver devices Familiarity with FPGA/CPLD design flow Familiarity with the Quartus design software Some familiarity with the Qsys design tool is helpful, but not required If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCICUSTOM. FPGA_OPCICUSTOM. <p>Customizing the 28-nm Hard IP for PCI Express</p>