Why does the Siemens* ModelSim* simulation stop unexpectedly when using the SDI II IP Multi-Rate Parallel loopback without an external VCXO design? - Why does the Siemens* ModelSim* simulation stop unexpectedly when using the SDI II IP Multi-Rate Parallel loopback without an external VCXO design? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the ModelSim* testbench fails when simulating the SDI II Multi-rate Parallel loopback without external VCXO design. Resolution To work around this problem, please update the testbench by connecting the gxb_tx_reconfig_xcvr_clk to the tb_test_control_rx_coreclk . This problem is fixed starting with Quartus® Prime Pro Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 15014746534 False ['SDI II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']