Why is the “o_rx_pause” width as double as the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP? - Why is the “o_rx_pause” width as double as the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and onward, you may see the “o_rx_pause” width as double the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP. This is due to the quanta value shifted by one extra bit. Resolution To work around this problem, follow the steps below. ) Change directory to “../[your design directory]/synth” directory. ) Open the file “eth_f_pause.sv” for the F-Tile Ethernet FPGA Hard IP and “eth_f_dr_tx_pause.sv” for the F-Tile Ethernet Multirate FPGA IP. ) Modify the file as listed below: [Original] : assign quanta_value =(EHIP_RATE == 0) ? (quanta_sync << 3) : (EHIP_RATE == 1) ? (quanta_sync << 3) : (EHIP_RATE == 2) ? (quanta_sync << 2) : (EHIP_RATE == 3) ? (quanta_sync << 2) : (EHIP_RATE == 4) ? (quanta_sync << 1) : {4'b000,quanta_sync} ; [Modified] : assign quanta_value =(EHIP_RATE == 0) ? (quanta_sync << 3) : (EHIP_RATE == 1) ? (quanta_sync << 3) : (EHIP_RATE == 2) ? (quanta_sync << 1) : (EHIP_RATE == 3) ? (quanta_sync << 2) : (EHIP_RATE == 4) ? (quanta_sync << 1) : {4'b000,quanta_sync} ; This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 16025567260 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 23.4 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']