Why are fall clock paths missing in the timing reports when targeting destination clocks in Quartus® Prime timing analyzer? - Why are fall clock paths missing in the timing reports when targeting destination clocks in Quartus® Prime timing analyzer? Description Due to a problem in the Quartus® Prime Pro Edition Timing Analyzer version 25.1.1 and earlier, fall clock paths are missing in timing reports when targeting destination clocks. The Report Timing task fails to include I/O paths if both set_output_delay and set_output_delay -fall_clock assignments are defined simultaneously. This problem affects timing reports generated through the Report Timing dialog box or the report_timing command when using the following arguments: -to_clock, -fall_to_clock, or -rise_to_clock, as well as -to, -rise_to, or -fall _to followed by a clock collection or clock names. This means that certain paths may be missing from the timing reports, potentially hiding I/O paths that do not meet timing requirements. However, all summary reports, such as the Setup Summary Report or the Timing Closure Summary, will remain correct and accurately reflect all paths. Resolution To work around this problem, use any path filters not mentioned above to capture the necessary paths in your timing analysis. This problem has been solved in Quartus® Prime Pro Edition software version 25.3. Custom Fields values: ['novalue'] Troubleshooting 14025537917 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 25.1 ['Agilex™ FPGA Portfolio', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']