Why don't I see the h2f_rst_n signal assert in HPS simulation? - Why don't I see the h2f_rst_n signal assert in HPS simulation? Description Due to a problem in the Quartus® II software BFM simulation model, asserting the " h2f_rst_n " signal does not drive the " h2f_rst_n " signal. This causes unexpected interconnect behavior and the Platform Designer interconnect logic is not reset. This problem affects simulation only. Resolution To work around this problem, follow these steps: Modify " INITIAL_RESET_CYCLES " parameter in "submodules/<qsys-system-name>_<HPS-instance-name>_fpga_interfaces.sv" file to greater than 0. Assign clock ( f2h_axi_clk ) to the " h2f_reset_inst " instance. Simulation Code: ---------------- altera_avalon_reset_source #( .ASSERT_HIGH_RESET(0), .INITIAL_RESET_CYCLES(0) <======== (1) change "0" to 100 such as .INITIAL_RESET_CYCLES(100) ) h2f_reset_inst ( .reset(h2f_rst_n), .clk(\'0) <======== (2) change \'0 to clock signal such as .clk( f2h_axi_clk ) ); ---------------- This problem has been fixed in Quartus® II software version 14.0. Custom Fields values: ['novalue'] Troubleshooting 2205811768 False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']