Why Does the Simplex RX/TX Design Example Fail During HSSI Support Logic Generation with a QHIP_IP_PROPERTY Case Sensitivity Error in F-Tile JESD204B IP? - Why Does the Simplex RX/TX Design Example Fail During HSSI Support Logic Generation with a QHIP_IP_PROPERTY Case Sensitivity Error in F-Tile JESD204B IP? Description Due to a problem in Quartus® Prime Pro Edition Design Software Version 25.3, the F-Tile JESD204B IP Simplex RX/TX example design may fail with the following error in compilation: "Cannot find QHIP_IP_PROPERTY tile_ip_sip_instances with value …..." Resolution To work around this compilation error, manually remove the QHIP_IP_PROPERTY assignment from the .qip file in the Design Example folder. Steps: Navigate to the following path in the Design Example directory: intel_jesd204b_gts_<data path>/example_design/ed_synth/ip/jesd_gts_ss<data path>/jesd_gts_ss_<data path>intel_jesd<data path>/ Open the QIP file: jesd_gts_ss_<data path>intel_jesd<data path>.qip Locate and remove the line containing the QHIP_IP_PROPERTY assignment. Save the file and retry the compilation. This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.3.1. Custom Fields values: Troubleshooting QS-5429 novalue ['Interfaces JESD204B (Primary)'] 25.3.1 25.3 ['Agilex™ 7 FPGAs and SoCs']