Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? - Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? Hello, I am trying to understand how Quartus implements shift registers on Altera FPGAs, and whether there is an equivalent mechanism to the LUT-based shift registers available on Xilinx devices (e.g., SRL16/SRLC32 on UltraScale+). On Xilinx UltraScale+, a multi-stage shift register (with no reset, single clock, simple shift pattern) is often inferred into an LUT configured as an SRL, which significantly reduces flip-flop usage and does not materially increase logic area. Does Quartus infer any LUT-based shift-register structure (analogous to Xilinx SRL16/SRLC32), or are shift registers always implemented using either: flip-flops, or MLAB / M20K RAM structures? Replies: Re: Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? Good observation — that behavior is expected. Quartus will infer RAM‑based shift registers when the RTL is compatible with the device memory architecture. In particular, adding a reset to the shift chain typically prevents inference into MLAB/M20K and leaves the implementation in flip‑flops. The Quartus document below explicitly call out that coding styles like asynchronous resets can block RAM inference and force FF implementations: https://docs.altera.com/r/docs/683641/25.3.1/quartus-prime-pro-edition-user-guide-design-optimization/guideline-remove-fitter-constraints?tocId=tmmzgVOTMhoEtv7TLENcLA Additionally, on HyperFlex devices (Stratix 10 / Agilex), inference thresholds are higher to preserve Hyper‑Retiming. Checkout the KDB below: https://community.altera.com/kb/knowledge-base/why-doesnt-my-shift-register-get-inferred-when-targeting-intel%C2%AE-stratix%C2%AE10-fpga-/340793 Regards, Richard Tan Replies: Re: Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? Thank you for the detailed information. I noticed that the synthesis tool does not infer deeper shift registers into MLAB or M20K when the RTL process includes a reset. However, when the shift-register process does not include a reset, the tool does infer them into memory blocks. Is this behavior always expected? Replies: Re: Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? Thank you for your clear explanation. I’d like to add a bit more detail regarding shift register inference on Altera FPGAs for clarity. You are correct—MLAB RAM (Memory Logic Array Block RAM) utilizes the 6-input LUTs in our newer device families (such as Cyclone V, Cyclone 10 GX, Arria 10, and Agilex), and serves as a distributed, small-capacity RAM resource. However, Quartus does not infer shift registers into MLABs in the same way Xilinx tools infer SRL16/SRLC32 primitives into LUTs. To summarize: There is currently no direct equivalent to Xilinx’s SRL16/SRLC32 LUT-based shift register in Altera FPGAs. Inference of shift registers in Quartus typically results in the use of flip-flops (FFs) within the logic array for shallow shift registers. For deeper shift registers, Quartus may infer RAM-based implementations (using MLAB or M20K blocks), but these are not dedicated shift register resources and do not provide the same area and resource efficiency as Xilinx SRLs. MLABs are well-suited for small RAM structures but are not natively configured as shift registers. We shall close the case. Replies: Re: Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL? Hi, LUT based RAM is named MLAB RAM in Altera FPGA. It's available with 6 input LUT logic elements, e.g. Cyclone V, Cyclone 10 GX, Arria 10, Agilex. It can be used to implement small RAM but apparently no shift registers. Regards Frank