Why does my Stratix IV Nios II design achieve a lower FMax in Quartus II 13.0 and later? - Why does my Stratix IV Nios II design achieve a lower FMax in Quartus II 13.0 and later? Description Due to a problem in the Quartus® II software version 13.0 and later, Nios® II designs using DSP block multipliers targeting Stratix® III and IV devices may achieve a lower FMax than in the Quartus II software version 12.1 and earlier. Resolution To workaround this issue in the Quartus II software version 13.1 either: Generate your Nios II design (or sub design) in Qsys from the Quartus II software version 12.1, and compile in 13.0 / 13.1 Configure your Nios II processor to use LE based multipliers (May only give a partial improvement) This problem is scheduled to be resolved in a future version of the Quartus II software Custom Fields values: ['novalue'] Troubleshooting novalue False ['Nios® II Processor'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']