Does the ATX PLL to fPLL spacing rule on Intel® Stratix®10 L-Tile and H-Tile devices apply to fPLLs in Core mode? - Does the ATX PLL to fPLL spacing rule on Intel® Stratix®10 L-Tile and H-Tile devices apply to fPLLs in Core mode? Description Yes. The ATX PLL to fPLL spacing rule on Intel® Stratix® 10 L-Tile and H-Tile devices applies to fPLLs in Core and transceiver modes. Resolution If you violate this rule with your fPLL in either mode, the Intel Quartus® Prime Software will issue a critical warning. Custom Fields values: ['novalue'] Troubleshooting 18010393575 False ['L-Tile H-Tile fPLL Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']