1G/10Gb Ethernet PHY FPGA IP - The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Arria® V GZ FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Stratix® V GS FPGA Stratix® V GX FPGA The 1G/10G Ethernet PHY FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard. The user can switch dynamically between the 1G and 10G PCS using the Transceiver Reconfiguration Controller IP core to reprogram the core. This IP core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT 6/7 shielded twisted-pair cables, and chip-to-chip interfaces. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless 1G/10Gb Ethernet PHY FPGA IP Key Features Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA Offering Brief No No No Yes Encrypted Verilog Arria® V GZ FPGA Arria® V ST SoC FPGA Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes Offering Brief Production a1JUi0000049UUsMAM What's Included Encrypted Verilog source code Ordering Information IP-10GBASEKRPHY; IP-10GMRPHY Digikey Mouser a1JUi0000049UUsMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). Altera Solutions