Why does the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Example generation fail when using the Intel® Quartus® Prime Pro Edition Software version 22.1 - Why does the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Example generation fail when using the Intel® Quartus® Prime Pro Edition Software version 22.1 Description The error "Error: can't read "rp_generated_name": no such variable " will be observed when generating the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Example using the Intel® Quartus® Prime Pro Edition Software version 22.1. The error is caused by attempting to generate the design example with Example Design Files " Synthesis " option enabled, but the " Simulation " option is not enabled. Resolution To work around this problem, ensure that both Simulation and Synthesis options are enabled before clicking the " Generate Example Design " button. This problem has been fixed starting in version 22.3 of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18022508848 False ['F-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']