Why does programming the flash memory fail on the Stratix® V FPGA Development Kit? - Why does programming the flash memory fail on the Stratix® V FPGA Development Kit? Description The examples provided in the " Creating Flash Files Using the Nios® II EDS " section of the Stratix® V GX FPGA Development Kit User Guide are incorrect. They use an incorrect address for user hardware 1. The Address Range given for User hardware 1 in Table A-1 Byte Address Flash Memory Map is: 0x020C.0000 to 0x0413.FFFF Resolution Use the following commands to generate flash files correctly: For .sof files: sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020C0000 --pfl --optionbit=0x00030000 --programmingmode=PSr For .elf files: elf2flash --base=0x0 --end=0x0FFFFFFF --reset=0x071C0000 --input=<yourfile>_sw.elf --output=<yourfile>_sw.flash --boot=/components/altera_nios2/boot_loader_cfi.srec Related Articles What is the correct flash offset when using the Stratix V GX FPGA Development Kit? Custom Fields values: ['novalue'] Troubleshooting 2205754504 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']