Why do I see unconstrained "am_muxsel_gen_inst|async_out" clocks within the Stratix® 10 E-Tile CPRI PHY IP core in timing report for example design? - Why do I see unconstrained "am_muxsel_gen_inst|async_out" clocks within the Stratix® 10 E-Tile CPRI PHY IP core in timing report for example design? Description When you compile Stratix® 10 E-Tile CPRI PHY IP example design in the Quartus® Prime Pro Edition software version 19.2, you will see below highlighted unconstrained clocks. dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[1].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[2].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out dut_wrapper|dut|alt_cpriphy_c3_0|SL_SOFT_I[3].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out Resolution These are not valid warnings. The nodes highlighted are not clocks. They are safe to be ignored. Custom Fields values: ['novalue'] Troubleshooting QS-299527 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']