Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file? - Why do the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP not appear in the .pin file?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.1 and earlier, the “n” leg of the transceivers within the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP do not appear in the .pin file. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 18.1.1.
Custom Fields values:
['novalue']
Troubleshooting
FB: 604183;
False
['Ethernet']
['FPGA Dev Tools Quartus® Prime Software Pro']
18.1.1
18.1
['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA']
['novalue']
['novalue']
['novalue'] - 2023-03-27
external_document