Why do I see functional failures on the paths involving High-Voltage IO bank input buffers in the Agilex™ 5 designs? - Why do I see functional failures on the paths involving High-Voltage IO bank input buffers in the Agilex™ 5 designs? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, you might see functional failures when compiling the Agilex™ 5 designs. A timing model miscorrelation in High Voltage I/O (HVIO) bank input buffers (IBUF) results in inaccurate timing analysis. The miscorrelation can range from 0.7 to 2.5 ns. The problem affects the Agilex™ 5 FPGA E-series and D-series designs using input pins in HVIO banks. High Speed I/O (HSIO) banks are not impacted. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Pro Edition Software version 24.2: Quartus® Prime Pro Edition Software v24.2 Patch 0.02 for Windows (.exe) Quartus® Prime Pro Edition Software v24.2 Patch 0.08 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v24.2 Patch 0.02 (.txt) The problem is fixed starting with the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 14022784861 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']