Design Evaluation for Timing Closure - 42 Minutes This training will teach you what to do when you have timing failures in your design, when your timing reports are red. You will learn how to review and evaluate compilation results in the Altera® Quartus® Prime Pro software v. 18.1 to identify problems that make the design fail timing. You will learn how to fix some of the problems. Course Objectives At course completion, you will be able to: Review compilation results to Identify problems Check details of specific failing paths Make changes to software settings or the RTL to close timing Skills Required An understanding of Basic FPGA design flow Asolid working knowledge of the Quartus II software Familiarity with the TimeQuest timing Analyzer Familiarity with Chip Planner If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSWTC02. FPGA_ODSWTC02. <p>Design Evaluation for Timing Closure</p>