Error(20054): Channel < * > has rsfec enabled, < * > is not a legal rsfec location, < * > are possible rsfec locations. - Error(20054): Channel < * > has rsfec enabled, < * > is not a legal rsfec location, < * > are possible rsfec locations. Description Due to the limitation of the CPRI Intel® FPGA IP core, you might see the error message above if you use more than one CPRI Intel® FPGA IP with RSFEC sharing in the Intel® Stratix® 10 FPGA E-tile and Intel Agilex® 7 FPGA E-tile. Resolution To work around this problem, avoid using the CPRI Intel® FPGA IP with RSFEC sharing. Another workaround is to separately generate and connect the MAC and PHY structure so that the PHY IP can share a single RS-FEC location. This problem will not be fixed in a future release of the CPRI Intel® FPGA IP core. Custom Fields values: ['novalue'] Troubleshooting 15012155342 False ['Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 20.4 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']