Why do I see recovery timing violations within the ALTLVDS_RX megafunction in my design? - Why do I see recovery timing violations within the ALTLVDS_RX megafunction in my design? Description You may see recovery timing violations on the reset path from your user-coded reset register through the rx_cda_reset port of the ALTLVDS_RX megafunction to the following signals *altlvds_rx_component|*auto_generated|rx*bit_slip_reg Address these paths by applying a set of set_multicycle_path assignments such as the ones below: set_multicycle_path -from [get_keepers <name of source node>] \ -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \ -setup -end 3 . set_multicycle_path -from [get_keepers <name of source node>] \ -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \ -hold -end 2 . The values of these assignments may vary depending on the relationship between the clock used for your external register and the rx_outclock port of the ALTLVDS_RX megafunction. Altera recommends using the rx_outclock port of the ALTLVDS_RX megafunction to clock the external reset register to synchronize the reset to the correct domain. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']