Why does the PCIe Gen3 testbench simulation not enter phase 2 or 3 of the equalization process? - Why does the PCIe Gen3 testbench simulation not enter phase 2 or 3 of the equalization process? Description The Altera® testbench bus functional model (BFM) for the Hard IP for PCI Express® does not support simulation of phase 2 or phase 3 equalization. Resolution Use a third party BFM to simulate these equalization phases, which the Hard IP supports. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']