Why does unexpected behavior occur in the Agilex™ 5 GTS PMA/FEC Direct PHY FPGA IP example design simulation compared to what is described in the simulation section of the GTS Transceiver PHY User Guide? - Why does unexpected behavior occur in the Agilex™ 5 GTS PMA/FEC Direct PHY FPGA IP example design simulation compared to what is described in the simulation section of the GTS Transceiver PHY User Guide? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, when the Soft Reset Controller (SRC) frequency is set to 10 GHz in simulation, certain delays and unexpected behaviors may be observed in the tx_pll_locked , rx_is_lockedtoref , rx_is_lockedtodata , tx_reset_ack , rx_reset_ack , tx_ready , rx_ready signals of the GTS PMA/FEC Direct PHY FPGA IP. Auto-recovery of the CDR lock lost will also be affected. Resolution Modify the simulation script by adding " +define+SIM_125MHz " as shown below in bold: i. VCS - modify run_vcs.sh : #VCS USER_DEFINED_ELAB_OPTIONS="-full64 +v2k -hsopt=gates +systemverilogext+.sv -sverilog -lca +lint=TFIPC-L +lint=PCWM -wreal res_def -xlrm coerce_nettype -timescale=1ps/1fs +vcs+vcdpluson +vpddrivers +define+TIMESCALE_EN +define+RTLSIM +define+SSM_SEQUENCE +define+QUARTUS +define+PFEDV_ONLY_MODEL_MACRO_DIS +define+SIM_125MHz +define+IP7521SERDES_UX_SIMSPEED +error+1000 +define+__SRC_TEST__ -debug_access+r+driver+f -debug_region+encrypt +rad -l vcs.log " #Verdi USER_DEFINED_ELAB_OPTIONS="-full64 +v2k -hsopt=gates +systemverilogext+.sv -sverilog -kdb -lca +lint=TFIPC-L +lint=PCWM -wreal res_def -xlrm coerce_nettype -timescale=1ps/1fs +vcs+vcdpluson +vpddrivers +define+TIMESCALE_EN +define+RTLSIM +define+SSM_SEQUENCE +define+QUARTUS +define+PFEDV_ONLY_MODEL_MACRO_DIS +define+SIM_125MHz +define+IP7521SERDES_UX_SIMSPEED +error+1000 +define+__SRC_TEST__ -debug_access+all -debug_access+r+driver+f -debug_region+encrypt +rad -l vcs.log " ii. VCSMX - modify run_vcsmx.sh : #VCS USER_DEFINED_ELAB_OPTIONS="+vcs+vcdpluson -debug_access -debug_region+encrypt " #Verdi USER_DEFINED_ELAB_OPTIONS="+vcs+vcdpluson -debug_access+all -debug_access -debug_region+encrypt" USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+TOP_LEVEL_ENTITY_INSTANCE_PATH=top_tst.top -timescale=1ps/1fs +define+SIM_125MHz +define+IP7521SERDES_UX_SIMSPEED" iii. Xcelium - modify run_xcelium.sh : USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+TOP_LEVEL_ENTITY_INSTANCE_PATH=top_tst.top +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SPEC_FORCE +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SIMULATION +define+IP7581SERDES_UXS2T1R1PGD_PIPE_FAST_SIM +define+IP7581SERDES_UX_SIMSPEED +define+SIM_125MHz +define+IP7521SERDES_UX_SIMSPEED" iv. Questasim - modify run_vsim.tcl : set TOP_LEVEL_NAME "top_tst" set USER_DEFINED_COMPILE_OPTIONS "+define+QUARTUS\ +define+PFEDV_ONLY_MODEL_MACRO_DIS\ +define+TIMESCALE_EN\ +define+RTLSIM\ +define+SSM_SEQUENCE\ +define+SIM_125MHz\ +define+IP7521SERDES_UX_SIMSPEED\ +define+__SRC_TEST__\ +incdir+./libraries" This problem will be fixed in a future version of the Quartus® Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting 16022870049 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']