What is the correct flash offset when using the Stratix V GX FPGA Development Kit? - What is the correct flash offset when using the Stratix V GX FPGA Development Kit? Description When following, "Creating Flash Files Using the Nios® II EDS" flow in the Stratix® V GX FPGA Development Kit User Guide, the following command is given: sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020A0000 --pfl --optionbit=0x00030000 --programmingmode=PS However, the Address Range given for User hardware 1 in Table A-1 Byte Address Flash Memory Map is: 0x020C.0000 to 0x0413.FFFF Hence the offset shown in the above command is incorrect. Resolution To correctly generate flash files, use the command below: sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020C0000 --pfl --optionbit=0x00030000 --programmingmode=PS Related Articles Why does programming the flash memory fail on the Stratix V FPGA Development Kit? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']