Why is there an unconstrained clock, altera_dual_boot: dual_boot_0|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot: alt_dual_boot|ru_clk? - Why is there an unconstrained clock, altera_dual_boot: dual_boot_0|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot: alt_dual_boot|ru_clk? Description Due to a problem in the Quartus® Prime Standard Edition Software version 15.1, you may see this warning message in the TimeQuest Timing Analyzer when using the Altera Dual Configuration IP. This problem is seen in design targetting MAX® 10 devices. Resolution To work around this problem, apply the following constraint in the sdc file create_generated_clock -name {ru_clk} -source [get_ports {clk}] -divide_by 2 -master_clock {clk} [get_registers {*ru_clk}] This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 16.0. Custom Fields values: ['novalue'] Troubleshooting FB: 322701; HSD: 2205838399 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 16.0 15.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']