SOC-02 - Embedded Software Development for Altera® SoCs - 2 Days - Enroll Now This comprehensive course provides embedded software engineers, hardware engineers, firmware developers, and system architects with an end-to-end, hands-on mastery of software development for the Hard Processor System (HPS) embedded in Altera® SoC FPGA devices — including the Cyclone® V SoC, Arria® V SoC, Arria 10 SoC, and Agile®x SoC families. The course is structured in three progressive tiers: • Foundation: Altera SoC architecture, boot flow, the ARM toolchain, the bare metal development environment, linker scripts, ARM MMU & cache management, interrupt handling, and robust fault management. • Integration & Production: HPS peripheral drivers, HPS-FPGA bridge interfacing and custom IP integration, DMA optimised data movement, FreeRTOS multi task development, Zephyr RTOS, U-Boot customisation, device tree authoring, and Linux kernel driver development. • Optional — Hardware/Software Co-Design: System partitioning methodologies, FPGA fabric accelerator design using RTL and HLS, advanced AXI communication fabrics and DMA, UIO/VFIO user space drivers, oneAPI FPGA compute, multi core AMP partitioning with OpenAMP, functional safety considerations, and full stack co-design validation. Course Content: 1. Altera SoC Architecture 2. HPS Subsystem Architecture 3. Boot Architecture 4. HPS Configuration 5. Quartus Prime and Platform Designer 6. BSP Generation 7. ARM Toolchain 8. Linker Scripts 9. MMU Fundamentals 10. Cache Management 11. JTAG Debugging 12. Interrupt Handling 13. Fault Management 14. HPS Peripheral Driver Development 15. HPS-FPGA Interfacing 16. Custom IP Drivers 17. DMA Integration 18. FreeRTOS on Cortex-A 19. Zephyr RTOS on Altera SoC Platforms 20. U-Boot 21. Device Tree 22. Linux Kernel Drivers 23. System Bring-Up 24. Co-Design Methodology [OPTIONAL] 25. System Partitioning [OPTIONAL] 26. FPGA Accelerator Development [OPTIONAL] 27. Advanced Communication [OPTIONAL] 28. Scatter-Gather DMA [OPTIONAL] 29. Memory Architecture [OPTIONAL] 30. User Space APIs [OPTIONAL] 31. Multi-Core AMP Partitioning [OPTIONAL] 32. OpenAMP [OPTIONAL] 33. System Validation [OPTIONAL] 34. Functional Safety [OPTIONAL] 35. Production Readiness [OPTIONAL] Prerequisites: - Proficiency in the C programming language — pointers, structs, bitwise operations, type punning, and memory mapped I/O. - Familiarity with embedded systems concepts: interrupts, memory maps, peripheral registers. - Basic understanding of ARM Cortex A or Cortex M architecture (register set, exception model). - Working knowledge of a Linux command line environment (shell commands, file system navigation, make, git). - Basic understanding of digital logic and FPGA concepts (fabric, IP blocks, AXI bus). Recommended: - Exposure to Altera Quartus Prime or Platform Designer (Qsys). - Some familiarity with an RTOS (FreeRTOS, ThreadX, Zephyr, or similar). - Basic knowledge of the Zephyr RTOS devicetree syntax and Kconfig build system is helpful but not required. For Optional Material: - Proficiency in at least one HDL (VHDL or SystemVerilog); familiarity with AMBA AXI protocol - Introductory knowledge of embedded Linux (kernel, device tree, driver concepts) - Awareness of functional safety standards Tools Required: - Quartus Prime Pro Edition - Altera SoC EDS - Ashling RiscFree IDE - Arm Development Studio - Altera HLS Compiler [OPTIONAL] - ModelSim-Altera / Questa [OPTIONAL] - GNU Arm Embedded Toolchain - Zephyr RTOS SDK - west (Zephyr meta-tool) - OpenOCD - FreeRTOS Kernel - U-Boot (Das U-Boot) - Linux Kernel - Yocto Project [OPTIONAL] - OpenAMP [OPTIONAL] - GNU Make / CMake - Python - Minicom / PuTTY Course Code: SOC 02. FA_SOC.