Why does the F-Tile Dynamic Reconfiguration Design Example in 400GE-4 FHT Base Variant with Enabled AN/LT fail to function correctly in hardware? - Why does the F-Tile Dynamic Reconfiguration Design Example in 400GE-4 FHT Base Variant with Enabled AN/LT fail to function correctly in hardware? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile Dynamic Reconfiguration Design Example in 400GE-4 FHT Base Variant with Enabled AN/LT will fail to function correctly in hardware. Specifically, after executing the tcl script to run the design example, the System Console will hang while displaying the following messages: Successfully Read Port 16 CSR Register offset = 0x142c0, data = 0x2006 Successfully Read ETHERNET ANLT Channel 16 Register anlt_seqcfg_csr4, offset = 0x2c0, data = 0x2006 Successfully Read Port 16 CSR Register offset = 0x240, data = 0x0 INFO: port_state value = 0x00000000 Successfully Read Port 16 CSR Register offset = 0x240, data = 0x0 INFO: port_state value = 0x00000000 Successfully Read Port 16 CSR Register offset = 0x240, data = 0x0 INFO: port_state value = 0x00000000 Successfully Read Port 16 CSR Register offset = 0x240, data = 0x0 INFO: port_state value = 0x00000000 Resolution To work around this problem in version 23.4 of the Quartus® Prime Pro Edition Software, perform the following steps : Change to the directory <design example project directory>/hardware_test_design/hwtest_f/eth_f_dr Open the file ftile_eth_anlt_cfgcsr_inc.tcl in a suitable text editor Locate the following snippet of code: proc get_reset_port_state_status_0 {ch} { puts "\tINFO: Channel $ch : Checking port state status..." set timeout 10 set i 0 while {1} { if {$ch > 0xf} { set rdata0 [reg_read [expr 0x200 + [expr $ch * 0x4]]] } else { set rdata0 [reg_read [expr 0xc0 + [expr $ch * 0x4]]] } puts $::fileid "\t\tINFO: port_state value = $rdata0" set port_state_value [expr ($rdata0 >> 29) & 0x1] if {($port_state_value == 1 ) || $i >= $timeout } break incr i } if {$port_state_value == 1} { puts "\tINFO: port_state signal is high " } else { puts "\tERROR: mport state does not go high" } } Change the following line FROM: set rdata0 [reg_read [expr 0x200 + [expr $ch * 0x4]]] TO: set rdata0 [reg_read [expr 0x200 + [expr [expr 0x0f & $ch] * 0x4]]] Save the file Run the design example in hardware using the modified script files in System Console This problem has been fixed starting in version 24.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16022618848 False ['Ethernet Subsystem IP (Early Access)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']