Why is the inconsistent phase shift requirement of coreclock for Intel® Arria® 10 LVDS in the handbook and IP GUI summary? - Why is the inconsistent phase shift requirement of coreclock for Intel® Arria® 10 LVDS in the handbook and IP GUI summary? Description Due to an error in LVDS Qsys GUI, it shows the core clock's phase is stuck at 0 degrees, while according to Intel® Arria® 10 handbook, it should be 180/SERDES factor. Resolution This problem is fixed starting with Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook version 18.0.1 Custom Fields values: ['novalue'] Troubleshooting 1408202585 False ['ALTLVDS_TX'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']