Why the RTL simulation is failing with PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP? - Why the RTL simulation is failing with PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, you might see the errors below when simulating the PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP with Input direction of the data pins in the group. [6625000000] Group0 -- READ, Repeat #0, Transfer #0: Expected: e0f0e3203e0f0e32 vs Actual: xxxxxxxx0000xxxx [6630000000] Group0 -- READ, Repeat #0, Transfer #1: Expected: e07871901e078719 vs Actual: xxxxxxxxxxxxxxxx Resolution To work around this problem, change the Pin type setting to Bidirectional mode to perform PHYlite simulation correctly. This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 22016256562 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']