Critical Warning: <slave_DDRx_instance_name>_pin_map.tcl: Failed to find PLL clock for pins mem_if|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_valid_predict[0].qvld_rd_address[0] - Critical Warning: <slave_DDRx_instance_name>_pin_map.tcl: Failed to find PLL clock for pins mem_if|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_valid_predict[0].qvld_rd_address[0] Description You will get the warning mentioned above in Quartus ® II software version 10.0SP1 and earlier if you have instantited <instance_name>_example_top.v for master and slave UniPHY controllers in your design. pll_dqs_ena_clk signal is missing in both master and slave <instance_name>_example_top.v and this will cause the critical warning in fitter report. To avoid the above mentioned critical warning, you should add pll_dqs_ena_clk port to the <instance_name> instantiated in the <instance_name>_example_top.v files for both master and slave module. For example, in top level design add the port pll_dqs_ena_clk as shown below: ddr2 mem_if ( .pll_ref_clk(pll_ref_clk), // when PHY is the PLL/DLL master, these will be outputs that can be shared with other components of the chip // when PHY is the PLL/DLL slave, these will be inputs from the PLL/DLL instantiations below .pll_afi_clk (pll_afi_clk), .pll_addr_cmd_clk (pll_addr_cmd_clk), .pll_dqs_ena_clk (pll_dqs_ena_clk), //added .pll_mem_clk (pll_mem_clk), .pll_write_clk (pll_write_clk), .pll_avl_clk (pll_avl_clk), .pll_config_clk (pll_config_clk), .pll_locked (pll_locked), .dll_delayctrl (dll_delayctrl), . . ); This issue has been fixed in Quartus II software version 10.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']