Why is the Configuration via Protocol (CvP) periphery image configuration time exceeding the PCIe 100 ms power-up-to-active time requirement? - Why is the Configuration via Protocol (CvP) periphery image configuration time exceeding the PCIe 100 ms power-up-to-active time requirement? Description In Intel® Quartus® Prime Pro Edition Software version 21.2, the CvP PCIe link might not be able to enumerate properly with Intel Agilex® 7 devices. This is because the periphery image configuration time exceeds the PCIe 100 ms power-up-to-active time requirement. Resolution To work around this problem, re-enumerate the PCIe link once the FPGA is successfully configured. This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509231256 , 1509261230 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']