Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks? - Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks? Description When compiling the DDR3, DDR2, LPDDR2, QDRII or RLDRAM II Controller with UniPHY IP using an FPGA device that has relatively low number of IO banks, you may experience a no-fit and possibly the following Quartus® II error. Error (175020): Illegal constraint of fractional PLL to the region The problem occurs if all the IO banks on a certain side of the FPGA have been fully used by the memory interface and the PLL input reference clock and other miscellaneous memory interface pins do not have the same IO standard as the memory interface IO. Resolution Set the PLL input reference clock and other miscellaneous memory interface pins to have same IO standard as the memory interface IO. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 10.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']