When using the Intel® Stratix® 10 FPGA E-tile Hard IP for Ethernet Intel® FPGA IP, oversized frame stripping can cause invalid frames to be presented to user logic. - When using the Intel® Stratix® 10 FPGA E-tile Hard IP for Ethernet Intel® FPGA IP, oversized frame stripping can cause invalid frames to be presented to user logic. Description When the E-tile Hard IP for Ethernet Intel® FPGA IP RX MAC receives frame size >= 65536, and enforce_max_frame_size is enabled, the frame output from RX MAC to user logic will be truncated to the frame size specified by max_rx_frame_size setting. A second invalid frame will output from RX MAC to user logic starting from byte-65536 to end of the super large frame. Resolution No workaround or fix is available for this errata problem. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 594222; True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']