Why are timing failures reported from *wys~ch3_pcs_chnl_hip_clk_out[0].reg for Intel® Arria® 10 PCIe* Gen3 Hard IP? - Why are timing failures reported from *wys~ch3_pcs_chnl_hip_clk_out[0].reg for Intel® Arria® 10 PCIe* Gen3 Hard IP? Description Due to a problem with the PCIe* Hard IP sdc file, when you use Intel® Arria® 10 PCIe* Hard IP Gen3, there will be following timing paths reported: from *altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg to other elements inside Hard IP. These paths can be safely ignored. Resolution To work around this problem, these paths can be ignored using the following set false path sdc assignments: set_false_path -from {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg} -to {*:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_common_pld_pcs_interface.inst_twentynm_hssi_common_pld_pcs_interface~pld_rate_reg.reg} set_false_path -from {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg} -to {*:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg} set_false_path -from {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg} -to {*:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg} set_false_path -from {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg} -to {*:phy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~tx_clk2_by2_1.reg} This problem will be resolved in a future release of the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting FB: 409116; False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']