MAX10 supported DDR3 topology - MAX10 supported DDR3 topology Hello, I am working on my first implementation of DDR3 memory with MAX10 FPGA. My initial direction was to follow MAX10 FPGA Development Kit with 10M50DAF484C8G on board. The main difference is - I would like to use only one DDR3 memory chip - IS43TR16640C-125JBLI - the never revision of the one used on the kit. BUT. In "Intel® MAX® 10 External Memory Interface User Guide" there is following information: 4.3.1. Intel MAX 10 Supported DDR2 or DDR3 Topology For DDR2 or DDR3/DDR3L, the external memory interface IP for Intel MAX 10 devices uses two capture clocks with two discrete devices . Figure 13. Supported Topology for DDR2 or DDR3 Memory Interfaces This figure shows the supported DDR2/DDR3 topology. One clock captures the lower 16 bit of data and the other clock captures the top 8 bit of data. The memory interface IP in Intel MAX 10 devices generates DDR2 or DDR3/DDR3L IPs targeted for this configuration only. Do I understand it correctly that it is not possible to use MAX 10 FPGA with single 16 bit DDR memory and If i want to use DDR3 I need to have second 8-bit part, even if my design requires 16 bits only? Thank you for support Replies: Re: MAX10 supported DDR3 topology I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: MAX10 supported DDR3 topology Hello, Yes you can. The ECC bit is only set to 8-bit. So you cannot use 4-bit as ECC. Regards, Adzim Replies: Re: MAX10 supported DDR3 topology Hello Adzim, Thank you for your reply. Does it mean that if I do not plan to use ECC I can use only 16-bit DDR3? The Table 3 "Supported Maximum External Memory Interface Width in Intel MAX 10 Device Packages" shows that device I am using (F484 package) can work with DDR3 "with or without" ECC. I know that not using ECC sounds weird, but I in fact I need 12 bits out of this 16-bit message, so I have 4 bits left for error correction. Replies: Re: MAX10 supported DDR3 topology Hello, Do I understand it correctly that it is not possible to use MAX 10 FPGA with single 16 bit DDR memory and If i want to use DDR3 I need to have second 8-bit part, even if my design requires 16 bits only? Yes, you need to create external memory interfaces to 16-bit SDRAM components with 8-bits error correction coding (ECC). Regards, Adzim