How do I enable polarity inversion on a per lane basis in the JESD204B Intel® FPGA IP? - How do I enable polarity inversion on a per lane basis in the JESD204B Intel® FPGA IP? Description When using the Avalon® memory mapped register interface in the JESD204B Intel® FPGA IP, you can enable polarity inversion through bit[0] of lane_ctrl_<n> registers (0x4 - 0x20) , where <n> represents the targeted lane number. Refer to the following links for JESD204B address map and register definitions: TX: https://www.intel.com/content/www/us/en/programmable/support/literature/ug/altera_jesd204_tx_regmap.html RX: https://www.intel.com/content/www/us/en/programmable/support/literature/ug/altera_jesd204_rx_regmap.html For designs that do not use the register interface, follow the instructions in the workaround under the Resolution section, to enable polarity inversion on a per lane basis in the JESD204B Intel® FPGA IP. Resolution If the JESD204B Intel® FPGA IP core register access is unavailable, perform the following workaround sequence to turn on polarity inversion: Change directory into <IP core name>/altera_jesd204_phy_<acds_version>/<sim or synth>/ Open the file <IP core name>_altera_jesd204_phy_<acds_version>_<random_string>.v with any text editor. Look for port .csr_lane_polarity in the inst_<tx and/or rx>_mlpcs instantiation. The width of the input port csr_lane_polarity is L, where L represents the total number of lanes in the JESD204B Intel® FPGA IP core. The LSB represents lane 0, the least significant 1 bit represents lane 1,..., MSB represents lane L-1. To enable polarity inversion, drive 1 to the targeted bit in the csr_lane_polarity input port. The following example shows an 8-lane design, with polarity inverted for lane 0 to lane 2: module <name>_altera_jesd204_phy_<acds_version>_<random_string> #( ... altera_jesd204_tx_mlpcs #( ... ) inst_tx_mlpcs ( ... .csr_lane_polarity (7'b0000_0111), // TX: polarity inverted for lanes 0-2 ... ); altera_jesd204_rx_mlpcs #( ... ) inst_rx_mlpcs ( ... .csr_lane_polarity (7'b0000_0111), // RX: polarity inverted for lanes 0-2 ... ); ... Custom Fields values: ['novalue'] Troubleshooting FB: 543356; False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']