Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly? - Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly? Description Due to a problem with the Intel® Quartus® Prime version 17.1 and earlier transceiver calibration code, Intel Arria® 10 and Intel Cyclone® 10 PCIe* PIPE PHYs configured for Gen1 and Gen2 configurations may fail to link train correctly and reach the L0 state. Resolution This problem has been fixed starting in Intel Quartus Prime v17.1.1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1.1 16.1.2 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']