Why does the Lane Equalization Control Register of the Intel® Arria® 10 PCIe* Hard IP store an incorrect initial preset value when operating as an endpoint in Gen3 mode? - Why does the Lane Equalization Control Register of the Intel® Arria® 10 PCIe* Hard IP store an incorrect initial preset value when operating as an endpoint in Gen3 mode? Description Due to a silicon problem, the Intel® Arria® 10 PCIe* Hard IP captures the initial “Transmitter Preset” and “Receiver Preset Hint” value from each received TS rather than from the EQ TS when operating as an endpoint in Gen3 mode, this causes the stored values of the “Upstream Port 8.0 GT/s Transmitter Preset” and “Upstream Port 8.0 GT/s Receiver Preset Hint” to be incorrect. Resolution No workaround for this Silicon problem is available. This problem does not impact link training and so can be safely ingored. Due to this problem, do not refer to the “Lane Equalization Control Register” to check the initial captured preset and preset hint when the Intel® Arria® 10 PCIe* Hard IP is operating as an endpoint in Gen3 mode. Custom Fields values: ['novalue'] Troubleshooting 2205693289 True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']