DisplayPort Simulation Example File Fails to Generate in Reduced Bit Rate (RBR) Mode - DisplayPort Simulation Example File Fails to Generate in Reduced Bit Rate (RBR) Mode Description The DisplayPort IP core does not assert the rx_vid_locked signal for designs in RBR mode. The receiver does not show any data. You will not be able to test your design in RBR mode in simulation. The simulation test eventually times out after a period of time. Resolution There is no workaround for this issue. This issue will be fixed in a future version of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']