What is the purpose of the HPS SoC out1_n and out2_n signals? - What is the purpose of the HPS SoC out1_n and out2_n signals? Description When routing the output of the HPS UART to the FPGA, extra signals (out1_n and out2_n) are generated. Due to a problem, the functionality of out1_n and out2_n is not described in the device handbook Resolution These two signals, out1_n, and out2_n, are user-designated outputs and can be set to an active low by programming the OUT1 or OUT2 bit of the MODEM Control Register to a high level. A Master Reset operation sets this signal to its inactive (high) state. This information is added starting with release 15.1 of the device handbook. Custom Fields values: ['novalue'] Troubleshooting n/a False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.1 12.1 ['Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']