DI2CMS - I2C Bus Interface - Master/Slave - Flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for both SMBus (System Management Bus) and PMBus (Power Management Bus… Based in Poland, European Union, our company provides Verilog and VHDL high quality synthesizable IP Cores of processors and microcontrollers, bus interfaces, arithmetic coprocessors and components… Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA The DI2CMS is a flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for both SMBus (System Management Bus) and PMBus (Power Management Bus) protocols. Designed to meet the latest I2C v3.0 specification, the DI2CMS core is composed of two primary modules: DI2CM (Master) and DI2CS (Slave), enabling operation as either a master or slave device on the bus. The core supports advanced I2C features such as multi-master arbitration, clock synchronization, and controller clock stretching, making it suitable for complex, multi-master environments. Transmission speeds are configurable up to 3.4 Mb/s, covering all standard I2C modes – Normal (100 kHz), Fast (400 kHz), Fast-plus (1 MHz), and High-Speed (3.4 MHz) – as well as all predefined SMBus and PMBus clock frequencies. Aerospace ASIC Proto Consumer Defense Government Industrial Medical Transportation DI2CMS - I2C Bus Interface - Master/Slave Key Features Conforms to the I2C v3.0 specification Offering Brief No No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Cyclone® III FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA Yes Yes 25.1.1 Offering Brief Production a1JUi0000049UAmMAM What's Included HDL Source Code Ordering Information DI2CMS a1JUi0000049UAmMAM Production Intellectual Property (IP) a1MUi00000BO8rgMAD a1MUi00000BO8rgMAD Select 2026-04-21T12:58:30.000+0000 Flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for both SMBus (System Management Bus) and PMBus (Power Management Bus) protocols. Partner Solutions