RapidIO II IP Core rx_cal_busy and tx_cal_busy Signals Have Wrong Direction - RapidIO II IP Core rx_cal_busy and tx_cal_busy Signals Have Wrong Direction Description In the initial version of the RapidIO II IP core, the rx_cal_busy and tx_cal_busy signals are erroneously declared as input signals. These signals should be output signals of the IP core. Resolution To fix this issue in your RapidIO II IP core variation, edit the top-level file < variation >.v and the top-level simulation file < variation >_sim/< variation >.v , or in the corresponding .vhd files, to declare these signals as output signals. The declarations are correct in the RapidIO II IP core internal modules. This issue is fixed in version 12.1 SP1 of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']