Why do compilation and timing fail when using the F-Tile Triple-Speed Ethernet FPGA IP Design Example? - Why do compilation and timing fail when using the F-Tile Triple-Speed Ethernet FPGA IP Design Example? Description Due to a problem in the F-Tile Triple-Speed Ethernet FPGA IP Design Example, compilation and timing are failing in the Quartus® Prime Pro Edition Software version 23.2. Resolution To workaround this problem, please download the attached altera-eth-tse-hw.zip and follow the below steps: 1: Extract the altera_eth_tse_hw.zip to altera_eth_tse_hw folder. 2: Copy these 3 files from altera_eth_tse_hw folder to <design_example_dir>/hardware_test_design folder. 3: Open Quartus® Prime Pro Edition Software version 23.2, open the project and select the <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf 4: On the Processing menu, click Start Compilation. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.3. Custom Fields values: ['novalue'] Troubleshooting 16021005197 False ['Triple-Speed Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.2 ['Agilex™ 7 FPGA F-Series'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']