Why does my Intel Agilex® FPGA I/O PLL fail to lock or have high jitter after being reconfigured? - Why does my Intel Agilex® FPGA I/O PLL fail to lock or have high jitter after being reconfigured? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, the Intel Agilex® FPGA I/O phase-locked loop (PLL) may fail or perform suboptimally on hardware after reconfiguration. This problem may occur when the reconfiguration .MIF is generated using the Platform Designer. The settings for bandwidth control, charge pump, and ripplecap are configured for Intel® Stratix® 10 devcies rather than for Intel Agilex® 7 devices. This problem affects both I/O bank and fabric-feeding PLLs but does not affect other device families. Resolution To work around this problem, manually set the bandwidth control, charge pump, and rippecap settings according to the Intel Agilex ® Clocking and PLL User Guide . This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15010462522 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 21.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']